Project Title: FPGA/SoC Design
Reconfigurable computing (RC) is increasingly being adopted for several application domains, from high-performance computing (HPC) to high-performance embedded computing (HPEC). RC is enabled by FPGA technology, which offers a highly parallel and flexible architecture for developing high-performance hardware accelerators and interfaces. FPGAs can be well suited to address the computational needs for next-generation apps and missions. However, due to low-level abstraction and hardware complexity, programmers are challenged to design for FPGAs.
For SURE 2019, the FPGA/SoC Team will provide professional training to guide students to the theory and practice of FPGA/SoC design. Initially, students will be trained, with concepts in FPGA/SoC architecture, tools, and development, with emphasis in hardware acceleration and interfaces. Next, without guidance, students will apply these concepts to address an independently chosen problem in the HPC or HPEC domains. At the concluding SURE EXPO, students will present the solutions to their chosen problem, and report their success for judging.
Research & Development Focus
- Hardware acceleration for FPGA/SoC platforms in HPC and embedded computing domains
- Hardware interfaces for embedded FPGA/SoC platforms
- HPC Division
FPGA acceleration for HPC FPGA accelerators
Tools: OpenCL, SDSoC, SDAccel, etc.
- Embedded Division
FPGA-hardware interfacing and glue logic
FPGA acceleration for embedded platforms
Tools: HLS, Vivado, XSDK, Petalinux, etc.
- Talented participants in the Embedded Division flow into P1
- Talented participants in the HPC Division flow into P2
- Required: some experience in VHDL or Verilog
- Required: some experience in FPGAs/SoCs
- Desirable: some experience in Linux
Computer Engineering, Electrical Engineering, and Computer Science
Students in this position will be volunteers.